This invention relates generally to semiconductor manufacture and testing. More particularly, this invention relates to a test carrier, a test method and a test system for testing semiconductor components.
Semiconductor components must be tested following the fabrication process. For testing small, thin components, such as bare dice and chip scale packages, test carriers can be utilized to temporarily package the components. One type of test is referred to as burn-in and involves heating a component for several hours while test signals are applied to integrated circuits on the component. This type of test carrier is disclosed in U.S. Pat. Nos. 5,519,332; 5,541,525; 5,495,179; 5,440,240; and 5,408,190 to Wood et al.
Typically the component being tested includes external contacts, such as bond pads on bare dice, or ball grid array (BGA) solder balls on chip scale packages. An interconnect component of the test carrier includes contacts for establishing temporary electrical connections with the external contacts on the component.
The test carrier also includes a base with terminal contacts that electrically connect to a test apparatus such as a test socket or test board. The test apparatus is in electrical communication with test circuitry configured to transmit test signals to the integrated circuits. During assembly of the carrier, separate electrical paths are formed between the terminal contacts on the base, and the contacts on the interconnect. One method for making these electrical paths is by forming the base and interconnect with metal conductors, and then wire bonding the conductors on the base, to conductors on the interconnect.
One aspect of these carrier is that the external contacts on semiconductor components are becoming smaller and more closely spaced. Accordingly, the electrical paths through the test carriers to the components are becoming more closely spaced. Also signal transmission speeds through the electrical paths are increasing. For example, some integrated circuits operate at clocking speeds of 500 mhz or more and must be tested at these speeds.
One problem occurring during testing at high speeds is referred to as xe2x80x9cparasitic inductancexe2x80x9d. For example, parasitic inductance can result from switching transients and cross coupling between the conductors on the base or interconnect of the test carrier. Parasitic inductance can also result from cross coupling of the bond wires between the interconnect and base. The parasitic inductance can cause spurious signals and a drop or modulation in the power supply voltage, that is sometimes referred to as power supply noise. Parasitic inductance, and the resultant spurious signals and power supply noise, can degrade the operation of the semiconductor component and adversely affect the test results.
The test circuitry typically includes decoupling capacitors to help alleviate parasitic inductance generated within the test circuitry. However, parasitic inductance can also occur in the electrical paths between the test circuitry and the test carrier. For example parasitic inductance can occur in the test socket or test board.
Another prior art method for reducing parasitic inductance and power supply noise is by mounting decoupling capacitors directly to the test socket. For example, semiconductor devices packaged in conventional packages, such as small outline j-lead packages (SOJs), or dual in-line packages (DIPs), are typically tested by insertion into sockets on the test board. For reducing parasitic inductance during testing, a thin film capacitor can be mounted between the socket and the semiconductor package. U.S. Pat. No. 5,844,419 to Akram et al., discloses a thin film capacitor configured for mounting to a test socket in direct electrical contact with the power and ground leads for the package.
Similarly, a thin film capacitor could be configured for insertion between the test board, and a test carrier for testing bare dice and chip scale packages. However, parasitic inductances can still arise within the test carrier. The present invention is directed to a test carrier which addresses the problem of parasitic inductance occurring within the test carrier.
In accordance with the present invention, an improved test carrier, test method, and test system for testing semiconductor components are provided. The test carrier can be used to temporarily package a semiconductor component, such as a bare die or chip scale package, for performing test procedures such as burn-in.
The test carrier includes a base for retaining the component, an interconnect for electrically contacting the component, and a force applying mechanism for biasing the component against the interconnect. The base includes terminal contacts, such as metal pins or balls, for electrically engaging mating electrical connectors on a test apparatus, such as a burn-in board. The interconnect includes interconnect contacts for electrically engaging external contacts on the component. In addition, conductors and bond pads on the base are wire bonded to conductors and bond pads on the interconnect to form separate electrical paths between the terminal contacts on the base, and the interconnect contacts.
The test carrier also includes at least one decoupling capacitor electrically connected to power (Vcc) and ground (Vss) paths through the carrier to the component. In a first carrier embodiment the capacitor is mounted within a recess formed in the base. In addition, the capacitor includes a first electrode electrically connected to a power terminal contact on the base, and a second electrode electrically connected to a ground terminal contact on the base. The first electrode is also electrically connected to an interconnect contact which electrically engages a power external contact on the component. Similarly, the second electrode is electrically connected to an interconnect contact which electrically engages a ground external contact on the component.
Electrical communication with the capacitor can be accomplished by soldering, wire bonding, TAB bonding, or conductive adhesive bonding the capacitor electrodes to pads on the base. In addition, an encapsulant, such as a curable polymer, can be formed in the recess to encapsulate and seal the capacitor. Alternately, the encapsulant can be omitted, and the base constructed with a capacitor socket for mounting the capacitor. The capacitor socket permits the base to be easily reconfigured with different capacitors for testing different types of components, or for performing different types of test procedures.
A second embodiment test carrier includes a lead frame molded to the base which forms internal conductors and terminal contacts for the carrier. During assembly of the test carrier, the decoupling capacitor is attached to the lead frame, and the lead frame and capacitor are molded into the base. A third embodiment test carrier includes a decoupling capacitor mounted to the interconnect rather than to the base. In this embodiment the capacitor can comprise a thin film capacitor, or alternately a surface mounted capacitor.
The test method includes the steps of: providing a test carrier comprising a decoupling capacitor contained in power and ground paths through the test carrier; assembling the test carrier with a semiconductor component therein; mounting the test carrier to a test apparatus; and then applying test signals through the test carrier to the component. During applying of the test signals, the capacitor reduces parasitic inductance and power supply noise transmitted to the component. In addition, electrical characteristics of the capacitor can be selected to optimize a particular test procedure, or testing of a particular component.
The test system includes the test carrier, a test apparatus for applying test signals to the test carrier, and test circuitry in electrical communication with the test apparatus for generating and analyzing the test signals. The test system applies test signals through the test apparatus, and through the test carrier to the component.